The present invention relates to a multi-level memory, in particular, to a semiconductor memory device for storing a multi-level, such as a multi-level flash memory, a multi-level EEPROM, and a multi-level EPROM.
As a memory cell of the EEPROM, those having a MOSFET structure where a charge storage layer (floating gate) and a control gate are laminated and formed on a semiconductor substrate are known. In general, the memory cell stores data of one bit in one cell by storing a "0" or "1" according the charge amount stored in the floating gate. In order to realize an EEPROM of a higher density, a multi-level memory method where data of multi bits are stored in one cell is known. For example, since data "0", "1", "2", "3" are stored in one cell in the four-level memory method, four charge amounts corresponding to the data are stored in the floating gate.
With an example of the four-level memory method, a configuration of the storage state of data will be explained.
With the floating gate charge amount of 0 defined to be the neutral state, a state where a positive charge with respect to the neutral state is defined to be the erasure state. The erasure state corresponds with the data "0". For example, by applying a high voltage (to 20 V) to a substrate with a control gate at 0 V, the erasure can be executed. A state where a negative charge amount with respect to the neutral state is defined to be the data "1" state. The data "2" state is also a state where a negative charge with respect to the neutral state is stored, but the negative charge amount is larger than the negative charge amount in the data "1" state. The data "3" state has further large negative charge amount.
For example, in the programming operation, with the substrate, source, drain having 0 V, and the control gate having a high voltage (to 20 V), a negative charge is stored in the floating gate so as to program the data "1", "2", "3". In the programming operation, with the substrate having 0 V, the source and drain having 10 V, and the control gate having a high voltage (to 20 V), a charge in the floating gate is retained so as to store the data "0", in the memory cell. Accordingly, four programming states ("0", "1", "2", "3") having threshold levels different from each other in the memory cell transistor can be realized in the memory cell.
As an example of a multi-level memory EEPROM, one where data of plural bits are programmed in a memory cell simultaneously as multi memory level data is known. In order to shorten the programming time, data of plural bits are programmed simultaneously. In this case, a plurality of data memory circuits are provided for programming multi-level data in the individual memory cells.
In order to accurately control the programming state, for example, the control data in the data memory circuit are converted such that the programming state of the memory cells is detected after the programming operation (programming verification), and if there is a memory cell with insufficient programming, a programming voltage is applied so as to promote programming only in the memory cell. By using the converted control data, the programming operation is executed again, and until all the selected memory cells are sufficiently programmed, the programming operation and the verification operation are executed.
However, the conventional multi-level memory EEPROM as mentioned above involves a problem due to the programming verification operation in addition to the time needed for actually storing a charge in a floating gate to prolong the total time necessary for programming. Particularly in the case whether each memory cell reached the programming state is detected independently, such as, first, whether the memory cell reached the "1" programming state is detected, and then whether the memory cell reached the "2" programming state is detected, the programming time will be extremely long by detecting all the programming state for each time. Besides, time needed for reaching the programming state for the memory cells differ from each other, that is, since the programming operation proceeds in order of "1", "2", "3", even when the easiest memory cell to program thereto reaches the "1" state, the other memory cells do not reach the "2" or "3" state, and thus it is totally meaningless to detect whether or not they reach the "2" or "3" state. That is, in the programming verifying operations, an unnecessary verifying operation is executed at the initial state of programming, thereby prolonging the programming time.
Since the control data are converted by executing the programming and verification, one data memory circuit has a plurality of sense circuits. In detecting a desired programming state with a plurality of sense circuits at the same time, sometimes a sense circuit detects that the programming is sufficient and another sense circuit detects that the programming is insufficient. This is due to the sensitivity difference caused by the irregularity of the transistor performance comprising the sense circuits. Therefore, sometimes the control data cannot be converted normally.
As heretofore mentioned, although the multi-level memory method is an effective means for achieving a high density, due to the difference in time necessary for each memory cell to reach the programming state, the programming time becomes too long since an unnecessary verify read is executed, thereby also prolonging the programming time for the programming verification. Further, by detecting the programming state of one memory cell with a plurality of sense circuits at the same time, the results may differ due to the sensitivity difference, thereby the reliability is ruined.